The invention relates to a process for producing a capacitor configuration.
In highly integrated memory devices, the information contents of the memory cells are, for example, recorded and provided through the use of appropriate capacitors. During the production of the memory devices or the memory cells on a semiconductor substrate, these capacitors are formed on the semiconductor substrate by using a structuring process and are wired appropriately. In the case of highly integrated circuits, the space required by the individual components, in particular therefore also the space required for the storage capacitors, is a significant factor.
It has therefore been proposed to form a plurality of substantially mutually independent storage capacitors in relation to an electrode in each case, for example the lower or bottom electrode, to be electrically connected to one another, so that the capacitors connected in this way can be formed physically particularly closely adjacent to one another, since specific contacts or lines can be used jointly and do not have to be formed multiple times. In this case, each capacitor is provided with its lower or bottom electrode on a carrier, on which, at least partly, a dielectric layer is provided, which is then followed, at least partly, by the separately provided upper or top electrodes. In order to develop the concept of the capacitor chain, an appropriate electrical connection has to be provided, for example in relation to the lower or bottom electrodes.
In known capacitor configurations having capacitor chains, in particular in the case of chain FeRAMs (Ferroelectric Random Access Memories) or CFRAMs (Chain Ferroelectric Random Access Memories), as they are called, it is a problem that the size of the storage capacitors cannot be below a specific minimum size of the storage capacitors, because of the functional reliability that needs to be provided. This applies even if, instead of a two-dimensional, planar capacitor configuration, three-dimensional capacitor configurations are provided by using corresponding side walls of three-dimensional structures.
In addition, when complying with all the rules on how to configure such a semiconductor component, it is currently not possible to achieve the necessary theoretical cell areas or capacitor areas. This is because the corresponding capacitors have to be formed larger than would be absolutely necessary, because of the production process.
It is accordingly an object of the invention to provide a process for producing a capacitor configuration, and a corresponding capacitor configuration, which overcome the above-mentioned disadvantages of the heretofore-known processes and configurations of this general type and in which the capacitors in the capacitor configuration are formed in a particularly space-saving way on a carrier.
With the foregoing and other objects in view there is provided, in accordance with the invention, a process for producing a capacitor configuration having a plurality of capacitors with a common contact region, the process includes the steps of:
forming a first electrode region on a surface region of a carrier;
forming at least one dielectric region at least partly on the first electrode region;
forming a common, substantially coherent second electrode region by directly applying an electrode material to the at least one dielectric region; and
forming a plurality of second electrodes by structuring the common, substantially coherent second electrode region such that the second electrodes are formed over regions of the first electrode region covered by the at least one dielectric region and such that the second electrodes are not in direct electrical contact with one another.
In other words, in the process for producing a capacitor configuration, in particular a memory device or the like having a plurality of capacitors on a carrier, in particular on a semiconductor substrate or the like, having a common contact region, at least one first electrode region is formed on a surface region of the carrier. Furthermore, at least one dielectric region is formed, at least partly, on the first electrode region. Furthermore, at least one second electrode region is formed, at least partly, on the dielectric region.
The process according to the invention for producing a capacitor configuration is characterized in that, on the first electrode region, on regions thereof covered by the dielectric region, a plurality of second electrode regions which are substantially at least not in direct electrical contact are formed.
It is therefore a basic idea of the process according to the invention to form a plurality of spatially separated and/or independent second electrode regions on a common first electrode region covered by a dielectric. Through the use of this procedure, a corresponding plurality of mutually closely adjacent capacitors is formed, the first common electrode region being used jointly by all the capacitors as one electrode, for example as a bottom electrode. The second electrode regions located opposite the first electrode region which, for example, is formed as a bottom electrode, are at least not in direct electrical contact with one another and thus in each case form the corresponding mating electrode for each capacitor in the plurality of capacitors. The advantage of this procedure, as compared with the prior art, is that it is no longer necessary for a separate first electrode region to be formed on the carrier for each individual capacitor in the capacitor configuration. The separation of the capacitors is therefore provided by the spatial separation of the second electrode regions with respect to their physical distance and with respect to their electrical insulation. This capacitor configuration or capacitor chain therefore substantially uses one electrode jointly, so that an additional connecting device needed in the prior art in the form of a connecting region or the like is not needed. In addition to possible further miniaturization and higher integration of the capacitor configuration, its production is thus also simplified since it is precisely the application or structuring of the additional connecting regions for the connected first electrodes or bottom electrodes that can be dispensed with. As a result, a corresponding lithography step or the like becomes obsolete.
According to a particularly preferred embodiment of a process according to the invention, provision is made for at least part of the plurality of second electrode regions to be formed by direct application of an appropriate electrode material to the respective dielectric region. In the case of this measure, therefore, the configuration of the second electrode regions is brought about directly through the use of the process of applying the appropriate material.
On the other hand, it is advantageous for at least part of the plurality of second electrode regions to be formed by applying a common and substantially coherent second electrode region to the dielectric region and then by subsequently structuring it. As opposed to the aforementioned procedure, therefore, here first of all a specific region of the dielectric region or else the entire dielectric region is substantially coherently coated with the material for the second electrode regions. The structuring of the individual separate second electrode regions is then carried out through the use of subsequent appropriate structuring, for example by using a mask/etching process.
In another embodiment of the process according to the invention, a plurality of dielectric regions that are substantially at least not in direct contact is formed on the first electrode region. This has the advantage that as a result of the provision of a plurality of separate and thus spatially separated dielectric regions, prestructuring on the first electrode region is carried out with regard to the second electrode regions to be formed.
The formation of the plurality of dielectric regions is advantageously carried out through the use of direct application of an appropriate dielectric material to the respective first electrode region. As a result, therefore, the configuration and selection of the dielectric regions is in each case already provided when the appropriate dielectric is applied.
On the other hand, it is advantageous for at least part of the plurality of dielectric regions to be formed by the application of a common and substantially coherent dielectric region to the respective first electrode region and by subsequent structuring. In this alternative or additional measure, therefore, firstly a coherent region is coated with the dielectric and the geometric configuration and formation of the separate dielectric regions is subsequently implemented through the use of appropriate structuring, for example by using a mask/etching process.
It is particularly preferred for at least part of the plurality of second electrode regions to be formed by the substantially flush and/or covering application of an appropriate electrode material on dielectric regions formed at least in the region of the first electrode regions. This is carried out in particular by a joint and/or simultaneous structuring of coherent dielectric regions and second electrode regions, the coherent dielectric regions being gradually formed on the first electrode region. This measure therefore achieves the situation in which, as an alternative to the procedure in which a plurality of mutually separated second electrode regions is formed on a coherent dielectric region, the second electrode regions are implemented substantially flush and coincident with the correspondingly formed dielectric regions. This can also be carried out, for example, by the first electrode region firstly being covered, at least partly, by a dielectric region and then subsequently covered with the material for the second electrode regions. The formation of the plurality of second separate electrode regions can then be carried out by appropriate simultaneous structuring of the second electrode regions and of the dielectric regions, if appropriate up to the surface of the first electrode regions.
In this case, it is additionally also advantageous if the first electrode region, according to a further embodiment of the process according to the invention, is structured, i.e. removed, in an intermediate region between adjacent second electrode regions and/or dielectric regions, in particular from a side facing away from the carrier, by forming, with a structuring step, connecting regions which connect respective first electrode regions, such that the intermediate region is substantially removed except for the connecting region and such that the respective first electrode regions are produced. This means that the plurality of capacitors is implemented by an appropriate pattern being cut into a coherent layer structure, including the first electrode region and the dielectric region and second electrode region provided over the first, so that second electrode regions which are independent and physically separate from one another are formed, for example as top electrodes or the like, the coherence of the first electrode region, which is provided on the carrier, and of the corresponding electrical contact being maintained.
The first electrode region is advantageously used as a common bottom electrode for the plurality of capacitors belonging to the capacitor device. Alternatively or additionally, provision is made for the second electrode regions to be used as separate top electrodes for the plurality of capacitors belonging to the capacitor configuration.
The process according to the invention is suitable in particular for the production of a capacitor configuration for a memory device having FeRAM cells or the like, in particular according to the chain capacitor principle, chain FeRAM or CFRAM cells.
A capacitor configuration produced according to the production process according to the invention and produced in particular for a memory device or the like, having a plurality of capacitors on a carrier, in particular a semiconductor substrate or the like, each capacitor having a bottom electrode provided on the carrier, a dielectric layer provided at least partly thereon and a separate top electrode provided at least partly thereon, and the capacitors having a common electrical connection in relation to the bottom electrode, is characterized in that the common electrical connection is formed as a substantially integral component part of a common first electrode region which forms the bottom electrode and substantially connects the latter electrically.
This measure achieves the situation where the plurality of capacitors belonging to the capacitor configuration have mutually electrically connected bottom electrodes, which are formed by the first electrode region. An additional electrical connection to be provided and, above all, its structuring within the context of the production process, are dispensed with.
The aspects of the invention and further properties and advantages of the process according to the invention, and also of the capacitor configuration according to the invention, are summarized below.
Particularly space-saving configurations of memory cells, in particular for ferroelectric memories, have been proposed within the context of the chain-FeRAM concept or CFRAM concept, as they are known. One advantage of this concept is that, as a result of the joint use of contacts, lines and/or electrodes by cells provided beside one another on the substrate, the cell area per stored information unit (per bit) can be greatly reduced. A theoretical limit of 4F2 per bit is specified. However, on the basis of production necessities, this theoretical lower limit cannot generally be reached. In this case, F represents the so-called minimum structure size of the technology respectively used. This is also referred to as the feature size. This structure size F is used in order to compare cell sizes in technologies employed in different ways.
In a similar way to that in DRAMs (Dynamic Randon Access Memories), a specific minimum size of the storage capacitors is also needed in CFRAMs for a reliable function of the memory cell configuration. This minimum size of the storage capacitors results in a specific minimum region for the capacitor electrodes. In specific technology generations, this minimum region can no longer be accommodated in a planar, that is to say two-dimensional, structuring of the memory cell. In order to be able to achieve this minimum region for these capacitors, a change to a three-dimensional structure is necessary, in which not only the bottom surface but also the side walls and side regions of the applied structures are employed and used. When such three-dimensional capacitors are provided in accordance with the current design rules in a regular array or a regular cell configuration, it is then no longer possible to achieve the theoretical cell area of 4F2, in particular in the case of a CFRAM.
Through the use of the procedure according to the invention presented, a process is provided with which the cell area per bit can be reduced considerably, with simultaneous technological simplification of the production procedure.
In the case of CFRAMs, it is always the case that at least two adjacent storage capacitors are connected to a common electrode, preferably to the lower electrode or bottom electrode. The conventional approach is to produce and form two individual capacitors next to one another on the carrier, it also being necessary to ensure appropriate electrical connection of the electrodes, which are initially separated.
The subject of the production process according to the invention is, as has already been described above, various procedures in which, for example, first of all a relatively extended, in particular elongate, capacitor is produced. From the latter, as has already been described above, for example the two necessary capacitors are produced by the removal of appropriate material layers. The distance between the adjacent capacitors can thus be reduced in relation to one another as compared with the prior art, which also results in a reduction in cell size. Furthermore, the production process for the conventionally necessary electrical connection of the bottom electrodes is dispensed with. A further level of lithography is dispensed with.
Viewed overall, through the use of the described production process according to the invention, the distance between adjacent capacitors belonging to the capacitor configuration is reduced and therefore the cell area per bit is reduced, such that it is additionally possible to leave out a level of lithography.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a process for producing a capacitor configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.